Integrated circuits are at the heart of today's modern computer. Integrated circuits have undergone extensive development for decades. Computer based development tools have greatly assisted in the ability to make these integrated circuits. It can be appreciated that complex integrated circuits are a result of many years of engineering and many years of developing design tools. However, the process of designing new and large integrated circuits is still a large effort and is typically very expensive because of all of the technicalities and details that need to be addressed.
For example, a design must typically consider signal and clock timing issues, manufacturing tolerances, operational changes due to changes in temperature and supply voltage fluctuations to name a few. Thus, the number of design constraints to be considered is expansive and this is why computer assisted design generally plays a big role. One issue that further complicated executing a design is that a complex integrated circuit design is often broken into design tasks of functional blocks such that different specialized design teams can concurrently work on the different tasks. Traditionally, these design groups retreat and work on each portion of the design and not until the design comes back together for “finalization” is timing again analyzed.
During a design process some function blocks may not be able to meet the initial specification and then the input/output specification of the function blocks may need to be altered. It can be seen that before completion of the design there may need to be many iterations in the process to achieve a design that will work properly. If such a design process is not closely and properly managed an integrated circuit design project can quickly go over budget.
Timing of signals in an integrated circuit design can be one of the most challenging design considerations. It can be appreciated in an average microprocessor integrated circuit there can be hundreds of thousands of signals propagating within the integrated circuit at any given time. Such signals must be synchronized such that they arrive at the intended destination at the appropriate time. Often timing is one of the last criteria analyzed by a design tool and if at this latter stage timing specifications are not met the design process might have to be revisited at various levels where many function blocks can require a redesign. It is very inefficient when designers must go back and change designs that have already been allocated space in the design and have been adjusted to pass simulation requirements, etc. It can be appreciated that the cost to design new integrated circuits or improve on old integrated circuit designs can be relatively expensive and current design tools and processes for integrated circuits that revisit timing at the end of the design process are less than perfect.
As stated above, integrated circuit design activities often occur in parallel, and when the design is nearly complete, then timing issues are analyzed. Thus, engineering groups will often think that they are done, and when timing is found to be unacceptable, then they must re-design their portion of the design. This can cause scheduling issues among other things for design teams and project managers. In traditional design practices, the global nature of the percentages of timing issues to be fixed by each function block design team was very pessimistic because different paths often pass through different numbers of function blocks. Macros can be considered as a program that creates and analyzes a functional block of an integrated circuit. Thus, a macro can operate on a file that contains the design for a particular function block of a section of the design. One macro can be worked on separately or independently of other macros, and the interface definitions of the macros allow data from multiple macros to be merged together for the final design product.
In some cases, it was possible that not all unacceptable path delays would be fixed in a second round of timing analysis, thus, requiring additional rounds of analysis and redesign to satisfy timing requirements before a design could be completed. Also, based on these inputs, designers often “overcompensate” or overshoot the new timing specification, where again, timing parameters are not met and an efficient design does not result. One traditional method for analyzing timing and generating timing feedback is to force each path through a macro to fix all of the failing slack seen by its parent, and to not allow a macro to worsen timing for paths that have acceptable timing at the parent level.
In other traditional methods, a designer might force each macro to fix a predefined amount of failing slack seen by its parent, such as one half (50%). However, these predefined parameters would be “global” in nature and the parameters would be applied to the timing feedback given to all interfaces of the function block. This method of correcting timing deficiencies is less than perfect and very limiting because any change made at the parent level of the hierarchy could cause very significant changes to the macro feedback assertions, no matter whether the change improved or degraded timing. These methods also results in overachieving on the correction of timing deficiencies.
Such “overcompensation” can often cause an inefficient circuit operation where devices are larger than required, and these devices could be smaller such that they consume less power. Generally, smaller devices provide for slower propagation of the signal. This implementation can degrade the efficiency of the design because the paths with acceptable slack were generally not analyzed for improved efficiency, once they were acceptable or positive. Accordingly, devices in these paths/circuits could not be reduced in size, making the path more efficient once the designer had acceptable timing.
Another traditional method for addressing timing solutions was to manually specify timing “contracts” between function blocks or macros based on an engineering judgment. These contracts were a manual attempt to divide cycle time of the clock domain between the various function blocks and the interconnect portions of a given path, based on human estimations. This method required a lot of manual intervention by designers and detailed knowledge of the design and layout of the components, or “floor plan”, of the integrated circuit. Critical knowledge is often unavailable at the time that the contracts are created and thus guesses or estimations had to be made. In addition, the contracts needed to be revisited and updated every time that a portion of the design was modified to ensure that timing remained acceptable. It can be appreciated that this traditional process was inefficient and error prone.
Another traditional design method includes defining default timing specifications or timing assertions for macros or function blocks. These default values generally included assumptions and generalizations made by experienced designers. An example, would be the general assumption that all macros inputs and outputs are latch bound such that the latches could be utilized to delay a signal when needed. Then, the default assertions could be defined to allow one third of the cycle time for the source macro, one third for the interconnect between macros, and one third for the sink macro. This can also lead to an inefficient design process and an inefficient design. This traditional method is a faster way to create a timing specification than other traditional methods that require time and effort to define timing contracts for all macros. However, it was also very error prone for many reasons.